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1 low power audio codec features system ? high performance and low power multi - bit delta - sigma audio adc and dac ? i 2 s/pcm master or slave serial data port ? two pairs of analog input with differential input option ? 256/384fs and usb 12/24 mhz system clocks ? sophisticated analog input and output routing, mixing and gain ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 92 db signal to noise ratio, - 85 db thd+n ? auto level control (alc) and noise gate dac ? 24- bit, 8 to 96 khz sampling frequency ? 93 db signal to noise ratio, - 85 db thd+n ? headphone driver capless mode ? bass or treble ? stereo enhancement ? pop and click noise suppression low power ? 1.8v to 3.3v operation ? 7 mw playback; 16 mw playback and record applications ? surveillance ? portable audio o rdering i nformation es83 88s -40 c ~ +85 c qfn -28 ES8388S
everest semiconductor confidential ES8388S revision 8 .0 2 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram ................................ ................................ ................................ ................... 4 2. pin out and descript ion ................................ ................................ ................................ 5 3. typical application circuit ................................ ................................ .......................... 6 4. power on reset ................................ ................................ ................................ ................ 6 5. clock modes and samp ling frequencies ................................ ............................... 7 6. micro - controller configura tion interface ................................ ...................... 8 7. digital audio interf ace ................................ ................................ ................................ 10 8. electrical character istics ................................ ................................ ...................... 11 absolute maximum rat ings ................................................................................................ 11 recommen ded operating condit ions .............................................................................. 11 adc analog and filte r characteristics an d specifications ........................................ 11 dac analog and filte r characteristics an d specifications ........................................ 12 power consumption ch aracteristics .............................................................................. 12 serial audio port sw itching specificatio ns ................................................................... 12 i 2 c switching specific ations ............................................................................................... 13 9. configuration regist er definition ................................ ................................ ........ 15 register 0 C chip control 1 , default 0000 01 0 0 ............................................................... 16 register 1 C chip control 2, default 0001 11 11 ............................................................... 16 register 2 C chip power managemen t, default 1100 0011 ........................................... 16 register 3 C adc power management , default 1 0 1 0 1100 ............................................ 17 register 4 C dac power management , default 1100 0000 ............................................ 17 register 5 C chip lo w power 1 , default 0000 0000 .......................................................... 17 register 6 C chip low power 2 , default 0000 0000 .......................................................... 17 register 7 C a nalog voltage management, default 1 111 1100 .................................. 17 register 8 C master mode control , default 1000 0000 ................................................. 18 register 9 C adc control 1, defau lt 0000 0000 ................................................................ 18 register 10 C adc control 2, defau lt 0000 0000 .............................................................. 18 register 11 C adc control 3 , default 0000 0 000 .............................................................. 18 register 12 C adc control 4 , default 0000 0000 .............................................................. 19 register 13 C adc control 5 , default 0000 0110 .............................................................. 19 register 14 C adc control 6 , default 001 0 0000 .............................................................. 19 register 15 C adc control 7 , default 0010 0000 .............................................................. 20 register 16 C adc control 8 , default 1100 0000 .............................................................. 20 register 18 C adc control 10 , default 0011 1000 ............................................................ 21 register 19 C adc control 11 , default 1011 0000 ............................................................ 21
everest semiconductor confidential ES8388S revision 8 .0 3 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 20 C adc control 1 2 , default 0011 0010 ............................................................ 21 register 21 C adc control 1 3 , default 0000 0110 ............................................................ 22 register 22 C adc control 1 4 , default 0000 0000 ............................................................ 22 register 23 C dac control 1, defau lt 0000 0000 .............................................................. 22 register 24 C dac control 2, defau lt 0000 0110 .............................................................. 23 register 25 C dac control 3 , default 001 0 0010 .............................................................. 23 register 26 C dac control 4, defau lt 1100 0000 .............................................................. 23 register 27 C dac control 5 , default 1100 0000 .............................................................. 24 register 28 C dac control 6 , default 0000 1000 .............................................................. 24 register 29 C dac control 7 , default 0000 0 000 .............................................................. 24 register 30 C dac control 8 , default 0001 1111 .............................................................. 24 register 31 C dac control 9 , default 1111 0111 .............................................................. 25 register 32 C dac control 10 , default 1111 1101 ............................................................ 25 register 33 C dac control 11 , default 1111 1111 ............................................................ 25 register 34 C dac control 12 , default 0001 1111 ............................................................ 25 register 35 C dac control 13 , default 1111 0111 ............................................................ 25 register 36 C dac control 14 , default 1111 1101 ............................................................ 25 register 37 C dac control 15 , default 1111 1111 ............................................................ 25 register 38 C dac control 16 , default 0000 0000 ............................................................ 25 register 39 C dac control 17 , default 0011 1000 ............................................................ 26 register 42 C dac control 20 , default 0011 1000 ............................................................ 26 register 43 C dac control 21 , default 000 1 0 000 ............................................................ 26 register 44 C dac control 22 , default 0000 0 000 ............................................................ 27 register 45 C dac control 23 , default 0000 0000 ............................................................ 27 register 48 C dac control 26 , default 0000 0000 ............................................................ 27 register 49 C dac control 27 , default 0000 0000 ............................................................ 27 register 53 C test mode, default 0000 0000 ..................................................................... 27 register 56 C adc test control 2, default 0000 0000 ..................................................... 27 10. package ................................ ................................ ................................ .......................... 28 11. corporate inform ation ................................ ................................ .......................... 29
everest semiconductor confidential ES8388S revision 8 .0 4 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram dvdd pvdd dgnd avdd agnd hpvdd hpgnd adcvref dacvref vmid mclk cdata cclk ce dsdin asdout sclk lrck lin2 lin1 rin1 rin2 i 2 c pga power supply i 2 s/pcm adc alc dac peq dac se stereo dac rout mono adc analog reference pga mixer hp driver lout pga lin1 lin2 clock mgr
everest semiconductor confidential ES8388S revision 8 .0 5 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 2. pin out and descript ion pin name i/o description 1 mclk i master clock 2 dvdd supply digital core supply 3 p vdd supply digital io supply 4 dgnd supply digital ground 5 s clk i/o audio data bit clock 6 dsdin i dac audio data 7 lrck i/o audio data left and right clock 8 asdo ut o adc audio data 9 nc no connect 10 dac vref o d ecoupling capacitor 11 lout o left analog output 12 rout o right analog output (same as left) 13 hpgnd supply ground for headphone output drivers 14 nc no connect 1 5 nc no connect 1 6 hpvdd supply supply for headphone output drivers 1 7 avdd supply analog supply 1 8 agnd supply analog ground 19 adc vref o d ecoupling capacitor 2 0 vmid o d ecoupling capacitor 2 1 rin 2 i right analog input 2 2 lin 2 i left analog input 2 3 rin1 i right analog input 2 4 lin1 i left analog input 2 5 nc no connect 26 c e i i 2 c d evice address selection 27 cdata i/o i 2 c data input or output 28 cclk i i 2 c clock input ES8388S mclk dvdd pvdd dgnd sclk dsdin lrck 1 2 3 4 5 6 7 rin2 vmid adcvref agnd avdd hpvdd nc 21 20 19 18 17 16 15 lin2 rin1 lin1 nc ce cdata cclk 22 23 24 25 26 27 28 nc hpgnd rout lout dacvref nc asdout 14 13 12 11 10 9 8
everest semiconductor confidential ES8388S revision 8 .0 6 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 3. typical application circuit 4. power on reset the device resets itself when dvdd (pin 2) ramp from ground voltage to supply voltage. the ground voltage needs to be less than 0.2v for proper reset. when dvdd voltage is removed, it is important to let it drop below 0.2v before next power up. an op tional discharge resistor (3.3k, for example) can be placed between dvdd and dgnd (pin 4). av dd i 2s_mclk i 2s_sclk i 2s_dsdi n i 2s_lrck i 2s_a sdo ut gn d i 2c/spi dat a i 2c/spi clk 1 uf + 22uf + 22uf 3 00 3 00 1 uf gn d mi c 2k gn d headphone j ack i 2c ad0 / sp i ce gn d av dd gn d gn d gn d 4.7uf 4.7uf 4.7uf 4.7uf gn d 1 k5 4.7uf gn d av dd 33 33 mc lk 1 dv dd 2 dg nd 4 pv dd 3 s clk 5 dsdi n 6 dl rc k 7 asd out 8 nc 9 hp vdd 16 nc 15 nc 14 hpg nd 13 rou t 12 lou t 11 av dd 17 ag nd 18 vmid 20 ri n2 21 lin2 22 rin1 23 lin1 24 nc 25 ce 26 cda ta 27 cclk 28 ad cvref 19 dac vref 10 gnd 29 ES8388S 1 uf 1 uf li n1 ri n1
everest semiconductor confidential ES8388S revision 8 .0 7 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 5. clock modes and samp ling frequencies the device supports two types of clocking: standard audio clocks (256fs, 384fs, 512fs, etc), and usb clocks (12/24 mhz). accor ding to the serial audio data sampling frequency (fs), the device can work in two speed modes: single speed mode or double speed mode. in single speed mode, fs normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally. lrck and sclk must be synchronously derived from the system clock with specific rates. the device can auto detect mclk/lrck ratio according to table 1. the device support s the mclk/lrck ratios listed in table 1. the lrck/sclk ratio is normally 64. table 1 slave mode sampling frequencies and mclk /lrck ratio speed mode sampling frequency mclk /lrck ratio single speed 8khz C 50khz 256, 384, 512, 768, 1024 double speed 50khz C 100khz 128, 192, 256, 384, 512 in master mode, lrck and sclk are derived internally from mclk. the available mclk/lrck ratios and sclk/lrck ratios are listed in table 2. table 2 master mode sampling frequen cies and mclk /lrck ratio mclk clkdiv2=0 mclk clkdiv2=1 adc sample rate (alrck) adcfsratio [4:0] dac sample rate (dlrck) dacfsratio [4:0] sclk ratio normal mode 12.288 mhz 24.576mhz 8 khz (mclk/1536) 01010 8 khz (mclk/1536) 01010 mclk/6 8 khz (mclk/1536) 01010 48 khz (mclk/256) 00010 mclk/4 12 khz (mclk/1024) 00111 12 khz (mclk/1024) 00111 mclk/4 16 khz (mclk/768) 00110 16 khz (mclk/768) 00110 mclk/6 24 khz (mclk/512) 00100 24 khz (mclk/512) 00100 mclk/4 32 khz (mclk/384) 00011 32 khz (mclk/384) 00011 mclk/6 48 khz (mclk/256) 00010 8 khz (mclk/1536) 01010 mclk/4 48 khz (mclk/256) 00010 48 khz (mclk/256) 00010 mclk/4 96 khz (mclk/128) 00000 96 khz (mclk/128) 00000 mclk/2 11.2896 mhz 22.5792mhz 8.0182 khz (mclk/1408) 01001 8.0182 khz (mclk/1408) 01001 mclk/4 8.0182 khz (mclk/1408) 01001 44.1 khz (mclk/256) 00010 mclk/4 11.025 khz (mclk/1024) 00111 11.025 khz (mclk/1024) 00111 mclk/4 22.05 khz (mclk/512) 00100 22.05 khz (mclk/512) 00100 mclk/4 44.1 khz (mclk/256) 00010 8.0182 khz (mclk/1408) 01001 mclk/4 44.1 khz (mclk/256) 00010 44.1 khz (mclk/256) 00010 mclk/4 88.2 khz (mclk/128) 00000 88.2 khz (mclk/128) 00000 mclk/2 18.432 mhz 36.864mhz 8 khz (mclk/2304) 01100 8 khz (mclk/2304) 01100 mclk/6 8 khz (mclk/2304) 01100 48 khz (mclk/384) 00011 mclk/6 12 khz (mclk/1536) 01010 12 khz (mclk/1536) 01010 mclk/6 16 khz (mclk/1152) 01000 16 khz (mclk/1152) 01000 mclk/6
everest semiconductor confidential ES8388S revision 8 .0 8 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 24 khz (mclk/768) 00110 24 khz (mclk/768) 00110 mclk/6 32 khz (mclk/576) 00101 32 khz (mclk/576) 00101 mclk/6 48 khz (mclk/384) 00011 8 khz (mclk/2304) 01100 mclk/6 48 khz (mclk/384) 00011 48 khz (mclk/384) 00011 mclk/6 96 khz (mclk/192) 00001 96 khz (mclk/192) 00001 mclk/3 16.9344 mhz 33.8688mhz 8.0182 khz (mclk/2112) 01011 8.0182 khz (mclk/2112) 01011 mclk/6 8.0182 khz (mclk/2112) 01011 44.1 khz (mclk/384) 00011 mclk/6 11.025 khz (mclk/1536) 01010 11.025 khz (mclk/1536) 01010 mclk/6 22.05 khz (mclk/768) 00110 22.05 khz (mclk/768) 00110 mclk/6 44.1 khz (mclk/384) 00011 8.0182 khz (mclk/2112) 01011 mclk/6 44.1 khz (mclk/384) 00011 44.1 khz (mclk/384) 00011 mclk/6 88.2 khz (mclk/192) 00001 88.2 khz (mclk/192) 00001 mclk/3 usb mode 12 mhz 24mhz 8 khz (mclk/1500) 11011 8 khz (mclk/1500) 11011 mclk 8 khz (mclk/1500) 11011 48 khz (mclk/250) 10010 mclk 8.0214 khz (mclk/1496) 11010 8.0214 khz (mclk/1496) 11010 mclk 8.0214 khz (mclk/1496) 11010 44.118 khz (mclk/272) 10011 mclk 11.0259 khz (mclk/1088) 11001 11.0259 khz (mclk/1088) 11001 mclk 12 khz (mclk/1000) 11000 12 khz (mclk/1000) 11000 mclk 16 khz (mclk/750) 10111 16 khz (mclk/750) 10111 mclk 22.0588 khz (mclk/544) 10110 22.0588 khz (mclk/544) 10110 mclk 24 khz (mclk/500) 10101 24 khz (mclk/500) 10101 mclk 32 khz (mclk/375) 10100* 32 khz (mclk/375) 10100* mclk 44.118 khz (mclk/272) 10011 8.0214 khz (mclk/1496) 11010 mclk 44.118 khz (mclk/272) 10011 44.118 khz (mclk/272) 10011 mclk 48 khz (mclk/250) 10010 8 khz (mclk/1500) 11011 mclk 48 khz (mclk/250) 10010 48 khz (mclk/250) 10010 mclk 88.235 khz (mclk/136) 10001 88.235 khz (mclk/136) 10001 mclk 96 khz (mclk/125) 10000 96 khz (mclk/125) 10000 mclk 6. micro - controller configura tion interface the device supports standard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to internal configuration registers. i 2 c interface is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. t he timing diagram for data transfer of this interface is given in figure 1 a and figure 1b . data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 4 00 kbps. a master controller initiates the transmission by sending a start signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 001000x, where x equals ad0. the rw bit indicates the slave data transfer dire ction. once an acknowledge bit is
everest semiconductor confidential ES8388S revision 8 .0 9 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by generating a stop signal, which is defined as a low -to - high tr ansition at sda while scl is high. in i 2 c interface mode, the registers can be written and read. the formats of write and read instructions are shown in table 1 and table 2 . please note that, to read data from a register, you must set r/w bit to 0 to a ccess the register address and then set r/w to 1 to read data from the register. table 3 write data to register in i 2 c interface mode chip address r/w register address data to be written start 001000 ad0 0 ack ram ack data ack stop figure 1a i 2 c write timing table 4 read data from register in i 2 c interface mode chip address r/w register address start 001000 ad0 0 ack ram ack chip address r/w data to be read start 001000 ad0 1 ack data nack stop figure 1b i 2 c read timing
everest semiconductor confidential ES8388S revision 8 .0 10 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 7. digital audio interface the device provides many formats of serial audio data interface to the input of the dac or output from the adc through lrck, bclk (sclk) and dacdat/adcdat pins. these formats are i 2 s, left justified, dsp/pcm and tdm mode. dac input dacdat is sampled by the device on the rising edge of sclk. adc data is out at adcdat on the falling edge of sclk. the relationship of sdata (dacdat/adcdat), sclk and lrck with these formats are shown through figure 2 to figure 6. n-2 n-1 n 3 2 1 1 n-2 n-1 n 3 2 1 1 figu re 2 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 n-2 n-1 n 3 2 1 figure 3 left justified serial audio data format up to 24 - bit figure 5 dsp/pcm mode a
everest semiconductor confidential ES8388S revision 8 .0 11 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 6 dsp/pcm mode b 8. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0.3v +5.0v input voltage range dgnd - 0.3v dvdd+0.3v operating temperature range -40 c +85 c storage temperature - 65 c +150 c recommended operatin g conditions parameter min typ max unit analog supply voltage level 2.0 3.3 3.6 v digital supply voltage level 1.6 1.8 3.6 v adc analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd=3.3v, dcvdd=1.8v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 85 92 95 db thd+n - 88 - 85 - 75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.1 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/3.3 vrms input impedance 20 k
everest semiconductor confidential ES8388S revision 8 .0 12 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com dac analog and filter ch aracteristics and sp ecifications test conditions are as the following unless otherwise specify: avdd=3.3v, dcvdd=1.8v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit dac performance signal to noise ratio (a - weigh) 83 93 95 db thd+n -85 -83 -75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.05 db filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 40 db de - emphasis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level avdd/3.3 vrms power consumption ch aracteristics parameter min typ max unit normal operation mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v: play back play back and record dvdd=3.3v, pvdd=3.3v, avdd=3.3v: play back play back and record 7 16 31 59 mw power down mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v dvdd=3.3v, pvdd=3.3v, avdd=3.3v tbd tbd mw serial audio port sw itching specificatio ns parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz
everest semiconductor confidential ES8388S revision 8 .0 13 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low tsclkl 15 ns sclk pulse width high tsclkh 15 ns sclk falling to lrck edge tslr C 10 10 ns sclk falling to sdout valid tsdo 0 ns sdin valid to sclk rising setup time tsdis 10 ns sclk rising to sdin hold time tsdih 10 ns figure 8 serial audio port timing i 2 c switching specific ations parameter symbol min max unit scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 ns sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 ns fall time scl t twf 300 ns
everest semiconductor confidential ES8388S revision 8 .0 14 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 i 2 c timing
everest semiconductor confidential ES8388S revision 8 .0 15 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 9. configuration regist er definition reg default b7 b6 b5 b4 b3 b2 b1 b0 0 0000 01 0 0 scpreset lrcm dacmclk samefs seqen enref vmidsel 1 0001 1 111 lpvcmmod lpvrefbuf pdnana pdnibiasgen vreflo pdnvrefbuf 2 1100 0011 adc_digpdn dac_digpdn adc_stm_rst dac_stm_rst adcvref_pdn dacvref_pdn 3 1 0 1 0 1100 pdnainl pdnadcl pdnadcbiasgen flashlp intlp 4 1100 0000 pdndacl pdndacr lout rout 5 0000 0000 lpdacl lpdacr lplout1 6 0000 0000 lppga lplmix lpadcvrp lpdacvrp 7 1 111 1100 vsel 8 1000 0000 msc mclkdiv2 bclk_inv bclkdiv 9 0000 0000 micampl 10 0000 0000 linsel capmode 11 0000 0110 ds ldcm tri 12 0000 0000 adclrp adcwl adcformat 13 0000 0110 adc_ratio_sel adcfsmode adcfsratio 14 001 0 0000 adc_invl adc_hpf_l maxgain[1:0] mingain[1:0] 15 001 0 0000 adcramprate adcsoftramp adcmute 16 1100 0000 ladcvol 18 0011 1000 alcsel maxgain[4:2] mingain[4:2] 19 1011 0000 alclvl alchld 20 0011 0010 alcdcy alcatk 21 0000 0110 alcmode alczc time_out win_size 22 0000 0000 ngth ngg ngat 23 0000 0000 daclrswap daclrp dacwl dacformat 24 0000 0110 mode_notch dac_ratio_sel dacfsmode dacfsratio 25 001 0 0010 dacramprate dacsoftramp dacler dacmute 26 1100 0000 ldacvol 27 1100 0000 rdacvol 28 0000 1000 deemp dac_invl dac_invr clickfree 29 0000 0 00 0 zerol zeror mono se vpp_scale 30/34 0001 1111 shelving_a[29:24]/shelving_b[29:24] 31/35 1111 0111 shelving_a[23:16]/shelving_b[23:16] 32/36 1111 1101 shelving_a[15:8]/shelving_b[15:8] 33/37 1111 1111 shelving_a[7:0]/shelving_b[7:0] 38 0000 0000 lmixsel rmixsel 39 0011 1000 ld2lo li2lo li2lovol mixboth 42 0011 100 0 rd2ro ri2ro ri2rovol 43 00 0 1 0 000 slrck lrck_sel offset_dis mclk_dis pdn_adc_anaclk pdn_dac_anaclk 44 00 00 0 000 offset 45 0000 0000 vroi 48 0000 0000 lrboth loutvol 49 0000 0000 routvol 53 0000 0000 testmodeenable 56 0000 0000 df2se_10db reg default b7 b6 b5 b4 b3 b2 b1 b0
everest semiconductor confidential ES8388S revision 8 .0 16 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 0 C chip control 1 , default 0000 01 0 0 bit name bit description scpreset 7 0 C normal (default) 1 C reset control port register to default lrcm 6 0 C alrck disabled when both adc disabled; dlrck disabled when both dac disabled (default) 1 C alrck and dlrck disabled when all adc and dac disabled dacmclk 5 0 C when samefs=1, adcmclk is the chip master clock source (default) 1 C when samefs=1, dacmclk is the chip master clock source samefs 4 0 C adc fs differs from dac fs (default) 1 C adc fs is the same as dac fs seqen 3 0 C internal power up sequence disable (default) 1 C internal power up sequence enable enref 2 0 C disable reference 1 C enable reference (default) vmidsel 1:0 00 C vmid disabled (default) 01 C 50 k ? divider enabled 10 C 500 k ? divider enabled 11 C 5 k ? divider enabled register 1 C chip control 2, default 0001 11 11 bit name bit description lpvcmmod 5 0 C normal (default) 1 C low power lpvrefbuf 4 0 C normal 1 C low power (default) pdnana 3 0 C normal 1 C entire analog power down (default) pdnibiasgen 2 0 C normal 1 C ibiasgen power down (default) vreflo 1 0 C normal 1 C low power (default) pdnvrefbuf 0 0 C normal 1 C power down (default) register 2 C chip power managemen t, default 1100 0011 bit name bit description adc_digpdn 7 0 C normal 1 C resets adc dem, filter and serial data port (default) dac_digpdn 6 0 C normal 1 C resets dac dsm, dem, filter and serial data port (default) adc_stm_rst 5 0 C normal (default) 1 C reset adc state machine to power down state dac_stm_rst 4 0 C normal (default) 1 C reset dac state machine to power down state adcvref_pdn 1 0 C adc analog reference power up 1 C adc analog reference power down (default) dacvref_pdn 0 0 C dac analog reference power up 1 C dac analog reference power down (default)
everest semiconductor confidential ES8388S revision 8 .0 17 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 3 C adc power management , default 1 0 1 0 1100 bit name bit description pdnainl 7 0 C normal 1 C left analog input power down (default) pdnadcl 5 0 C left adc power up 1 C left adc power down (default) pdnadcbiasgen 2 0 C normal 1 C power down (default) flashlp 1 0 C normal (default) 1 C adc low power intlp 0 0 C normal (default) 1 C low power register 4 C dac power management, default 1100 0000 bit name bit description pdndacl 7 0 C left dac power up 1 C left dac power down (default) pdndacr 6 0 C right dac power up 1 C right dac power down (default) lout 3 0 C lout disabled (default) 1 C lout enabled rout 2 0 C rout disabled (default) 1 C rout enabled register 5 C chip low power 1 , default 0000 0000 bit name bit description lpdacl 7 0 C normal (default) 1 C low power lpdacr 6 0 C normal (default) 1 C low power lplout1 3 0 C normal (default) 1 C low power register 6 C chip low power 2 , default 0000 0000 bit name bit description lppga 7 0 C normal (default) 1 C low power lplmix 6 0 C normal (default) 1 C low power lpadcvrp 1 0 C normal (default) 1 C low power lpdacvrp 0 0 C normal (default) 1 C low power register 7 C a nalog voltage management, default 1 111 1100 bit name bit description vsel 7:0 11111100 C normal (default)
everest semiconductor confidential ES8388S revision 8 .0 18 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 8 C master mode control , default 1000 0000 bit name bit description msc 7 0 C slave serial port mode 1 C master serial port mode (default) mclkdiv2 6 0 C mclk not divide (default) 1 C mclk divide by 2 bclk_inv 5 0 C normal (default) 1 C bclk inverted bclkdiv 4:0 00000 C master mode bclk generated automatically based on the clock table (default) 00001 C mclk/1 00010 C mclk/2 00011 C mclk/3 00100 C mclk/4 00101 C mclk/6 00110 C mclk/8 00111 C mclk/9 01000 C mclk/11 01001 C mclk/12 01010 C mclk/16 01011 C mclk/18 01100 C mclk/22 01101 C mclk/24 01110 C mclk/33 01111 C mclk/36 10000 C mclk/44 10001 C mclk/48 10010 C mclk/66 10011 C mclk/72 10100 C mclk/5 10101 C mclk/10 10110 C mclk/15 10111 C mclk/17 11000 C mclk/20 11001 C mclk/25 11010 C mclk/30 11011 C mclk/32 11100 C mclk/34 others C mclk/4 register 9 C adc control 1, defau lt 0000 0000 bit name bit description micampl 7:4 left channel pga gain 0000 C 0 db (default) 0001 C +3 db 0010 C +6 db 0011 C +9 db 0100 C +12 db 0101 C +15 db 0110 C +18 db 0111 C +21 db 1000 C +24 db register 10 C adc control 2, defau lt 0000 0000 bit name bit description linsel 7:6 channel input select 00 C lin1 (default) 01 C lin2 10 C reserved 11 C l - r differential input, l/r selection refer to ds (reg0xb[7]) capmode 0 0 C cap mode disabled (default) 1 C cap mode enabled register 11 C adc control 3 , default 0000 0 000 bit name bit description ds 7 differential input select 0 C from input lin1 - rin1 (default) 1 C from input lin2 - rin2 ldcm 6 adc dc measure
everest semiconductor confidential ES8388S revision 8 .0 19 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 0 C disable (default) 1 C enable tri 2 0 C asdout is adc normal output (default) 1 C asdout tri - stated, alrck, dlrck and sclk are inputs register 12 C adc control 4 , default 0000 0000 bit name bit description adclrp 5 i2s or left justified mode: 0 C left and right normal polarity 1 C left and right inverted polarity dsp/pcm mode: 0 C msb is available on 2nd bclk rising edge after alrck rising edge 1 C msb is available on 1st bclk rising edge after alrck rising edge adcwl 4:2 000 C 24 - bit serial audio data word length(default) 001 C 20- bit serial audio data word length 010 C 18- bit serial audio data word length 0 11 C 16- bit serial audio data word length 100 C 32- bit serial audio data word length adcformat 1:0 00 C i2s serial audio data format(default) 01 C left justify serial audio data format 10 C reserved 11 C dsp/pcm mode serial audio data format register 13 C adc control 5 , default 0000 0110 bit name bit description adc_ratio_sel 6 adc ratio selection for slave mode 0 C adc ratio auto detect (default) 1 C adc ratio use adcfsratio adcfsmode 5 0 C single speed mode (default) 1 C double speed mode adcfsratio 4:0 master mode adc mclk to sampling frequency ratio 00000 C 128 00001 C 192 00010 C 256 00011 C 384 00100 C 512 00101 C 576 00110 C 768 (default) 00111 C 1024 01000 C 1152 01001 C 1408 01010 C 1536 01011 C 2112 01100 C 2304 10000 C 125 10001 C 136 10010 C 250 10011 C 272 10100 C 375 10101 C 500 10110 C 544 10111 C 750 11000 C 1000 11001 C 1088 11010 C 1496 11011 C 1500 other C reserved register 14 C adc control 6 , default 001 0 0000 bit name bit description adc_invl 7 0 C normal (default) 1 C left channel polarity inverted
everest semiconductor confidential ES8388S revision 8 .0 20 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com adc_hpf_l 5 0 C disable adc left channel high pass filter 1 C enable adc left channel high pass filter (default) maxgain[1:0] 3:2 alc maxgain[1:0] for pga max gain 00000 C - 6.5db 00001 C - 5 db 00010 C - 3.5db 00011 C - 2db 00100 C - 0.5db 00101 C +1db 00100 C +2.5db 00111 C +4db 01000 C +5.5db 01001 C +7db 01010 C +8.5db 01011 C +10db 01100 C +11.5db 01101 C +13db 01110 C +14.5db 01111 C +16db 10000 C +17.5db 10001 C +19db 10010 C +20.5db 10011 C +22db 10100 C +23.5db 10101 C +25db 10110 C +26.5db 10111 C +28db 11000 C +29.5db 11001 C +31db 11010 C +32.5db 11011 C +34db others C +35.5db mingain[1:0] 1:0 alc mingain[1:0] for pga min gain 00000 C - 12db 00001 C - 10.5 db 00010 C - 9db 00011 C - 7.5db 00100 C - 6db 00101 C - 4.5db 00100 C - 3db 00111 C - 1.5db 01000 C 0db 01001 C +1.5db 01010 C +3db 01011 C +4.5db 01100 C +6db 01101 C +7.5db 01110 C +9db 01111 C +10.5db 10000 C +12db 10001 C +13.5db 10010 C +15db 10011 C +16.5db 10100 C +18db 10101 C +19.5db 10110 C +21db 10111 C +22.5db 11000 C +24db 11001 C +25.5db 11010 C +27db 11011 C +28.5db others C +30db register 15 C adc control 7 , default 001 0 0000 bit name bit description adcramprate 7:6 00 C 0.5 db per 4 lrck digital volume control ramp rate (default) 01 C 0.5 db per 8 lrck digital volume control ramp rate 10 C 0.5 db per 16 lrck digital volume control ramp rate 11 C 0.5 db per 32 lrck digital volume control ramp rate adcsoftramp 5 0 C disabled digital volume control soft ramp 1 C enabled digital volume control soft ramp (default) adcmute 2 0 C normal (default) 1 C mute adc digital output register 16 C adc control 8 , default 1100 0000 bit name bit description ladcvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to C 96 db. 00000000 C 0 db 00000001 C - 0.5 db
everest semiconductor confidential ES8388S revision 8 .0 21 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 00000010 C - 1 db 11000000 C - 96 db (default) register 18 C adc control 10 , default 0011 1000 bit name bit description alcsel 7:6 00 C alc off other C alc on maxgain[4:2] 5:3 set maximum gain of pga 000 C - 6.5 db 001 C - 0.5 db 010 C 5.5 db 011 C 11.5 db 100 C 17.5 db 101 C 23.5 db 110 C 29.5 db 111 C 35.5 db mingain[4:2] 2:0 set minimum gain of pga 000 C - 12 db 001 C - 6 db 010 C 0 db 011 C +6 db 100 C +12 db 101 C +18 db 110 C +24 db 111 C +30 db register 19 C adc control 11 , default 1011 0000 bit name bit description alclvl 7:4 alc target 0000 C - 16.5 db 0001 C - 15 db 0010 C - 13.5 db 0111 C - 6 db 1000 C - 4.5 db 1001 C - 3 db 1010 - 1111 C - 1.5 db alchld 3:0 alc hold time before gain is increased 0000 C 0ms 0001 C 2.67ms 0010 C 5.33ms (time doubles with every step) 1001 C 0.68s 1010 or higher C 1.36s register 20 C adc control 1 2 , default 0011 0010 bit name bit description alcdcy 7:4 alc decay (gain ramp up) time, alc mode/limiter mode: 0000 C 410 us/90.8 us 0001 C 820 us/182us 0010 C 1.64 ms/363us (time doubles with every step) 1001 C 210 ms/46.5 ms 1010 or higher C 420 ms/93 ms alcatk 3:0 alc attack (gain ramp down) time, alc mode/limiter mode: 0000 C 104 us/22.7 us 0001 C 208 us/45.4 us 0010 C 416 us/90.8 us
everest semiconductor confidential ES8388S revision 8 .0 22 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com (time doubles with very step) 1001 C 53.2 ms/11.6 ms 1010 or higher C 106 ms/23.2 ms register 21 C adc control 1 3 , default 0000 0110 register 22 C adc control 1 4 , default 0000 0000 bit name bit description ngth 7:3 noise gate threshold 00000 C - 76.5 dbfs 00001 C - 75 dbfs 11110 C - 31.5 dbfs 11111 C - 30 dbfs ngg 2:1 noise gate type x0 C pga gain held constant 01 C mute adc output 11 C reserved ngat 0 noise gate function enable 0 C disable 1 C enable register 23 C dac control 1, defau lt 0000 0000 bit name bit description daclrswap 7 0 C normal 1 C left and right channel data swap daclrp 6 i2s or left justified mode: 0 C left and right normal polarity 1 C left and right inverted polarity dsp/pcm mode: 0 C msb is available on 2nd bclk rising edge after alrck rising edge 1 C msb is avail able on 1st bclk rising edge after alrck rising edgelrck polarity dacwl 5:3 000 C 24- bit serial audio data word length 001 C 20- bit serial audio data word length 010 C 18- bit serial audio data word length bit name bit description alcmode 7 determines the alc mode of operation: 0 C alc mode (normal operation) 1 C limiter mode. alczc 6 alc uses zero cross detection circuit. 0 C disable (recommended) 1 C enable time_out 5 zero cross time out 0 C disable (default) 1 C enable win_size 4:0 windows size for peak detector set the window size to n*16 samples 00110 C 96 samples (default) 00111 C 102 samples .. 11111 C 496 samples
everest semiconductor confidential ES8388S revision 8 .0 23 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 011 C 16- bit serial audio data word length 100 C 32 - bit serial audio data word length dacformat 2:1 00 C i2s serial audio data format 01 C left justify serial audio data format 10 C reserved 11 C dsp/pcm mode serial audio data format register 24 C dac control 2, defau lt 0000 0110 bit name bit description mode_notch 7 notch mode, there is 2fs osr for input data 0 C notch mode disable (default) 1 C notch mode enable dac_ratio_sel 6 dac ratio selection for slave mode 0 C dac ratio auto detect (default) 1 C dac ratio use dacfsratio dacfsmode 5 0 C single speed mode (default) 1 C double speed mode dacfsratio 4:0 master mode dac mclk to sampling frequency ratio 00000 128; 00001 192; 00010 256; 00011 384; 00100 512; 00101 576; 00110 768; (default) 00111 1024; 01000 1152; 01001 1408; 01010 1536; 01011 2112; 01100 2304; 10000 125; 10001 136; 10010 250; 10011 272; 10100 375; 10101 500; 10110 544; 10111 750; 11000 1000; 11001 1088; 11010 1496; 11011 1500; other reserved. register 25 C dac control 3 , default 001 0 0010 bit name bit description dacramprate 7:6 00 C 0.5 db per 4 lrck digital volume control ramp rate (default) 01 C 0.5 db per 32 lrck digital volume control ramp rate 10 C 0.5 db per 64 lrck digital volume control ramp rate 11 C 0.5 db per 128 lrck digital volume control ramp rate dacsoftramp 5 0 C disabled digital volume control soft ramp 1 C enabled digital volume control soft ramp (default) dacler 3 0 C normal (default) 1 C both channel gain control is set by dac left gain control register dacmute 2 0 C normal (default) 1 C mute analog outputs for both channels register 26 C dac control 4, defau lt 1100 0000 bit name bit description ldacvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to C 96 db. 00000000 C 0 db
everest semiconductor confidential ES8388S revision 8 .0 24 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 00000001 C - 0.5 db 00000010 C - 1 db 11000000 C - 96 db (default) register 27 C dac control 5 , default 1100 0000 bit name bit description rdacvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to C 96 db. 00000000 C 0 db 00000001 C - 0.5 db 00000010 C - 1 db 11000000 C - 96 db (default) register 28 C dac control 6 , default 0000 1000 bit name bit description deemphasismode (deemp) 7:6 00 C de - emphasis frequency disabled (default) 01 C 32 khz de - emphasis frequency in single speed mode 10 C 44.1 khz de - emphasis frequency in single speed mode 11 C 48 khz de - emphasis frequency in single speed mode dac_invl 5 0 C normal dac left channel analog output no phase inversion (default) 1 C normal dac left channel analog output 180 degree phase inversion dac_invr 4 0 C normal dac right channel analog output no phase inversion (default) 1 C normal dac right analog output 180 degree phase inversion clickfree 3 0 C disable digital click free power up and down 1 C enable digital click free power up and down (default) register 29 C dac control 7 , default 0000 0 000 bit name bit description zerol 7 0 C normal (default) 1 C set left channel dac output all zero zeror 6 0 C normal (default) 1 C set right channel dac output all zero mono 5 0 C stereo (default) 1 C mono (l+r)/2 into dacl and dacr se 4:2 se strength 000 C 0 (default) 111 C 7 vpp_scale 1:0 00 C vpp set at 3.5v (0.7 modulation index) (default) 01 C vpp set at 4.0v 10 C vpp set at 3.0v 11 C vpp set at 2.5v register 30 C dac control 8 , default 0001 1111 bit name bit description shelving_a[29:24] 5:0 30- bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
everest semiconductor confidential ES8388S revision 8 .0 25 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 31 C dac control 9 , default 1111 0111 bit name bit description shelving_a[23:16] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 32 C dac control 10 , default 1111 1101 bi t name bit description shelving_a[15:8] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 33 C dac control 11 , default 1111 1111 bit name bit description shelving_a[7:0] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 34 C dac control 12 , default 0001 1111 bit name bit description shelving_b[29:24] 5:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 35 C dac control 13 , default 1111 0111 bit name bit description shelving_b[23:16] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 36 C dac control 14 , default 1111 1101 bit name bit description shelving_b[15:8] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 37 C dac control 15 , default 1111 1111 bit name bit description shelving_b[7:0] 7:0 30 - bit a coefficient for shelving filter default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} register 38 C dac control 16 , default 0000 0000 bit name bit description lmixsel 5:3 left input select for output mix 000 C lin1 (default) 001 C lin2 010 C df2se out 011 C adc input (after mic amplifier) others C reserved rmixsel 2:0 right input select for output mix 000 C rin1 (default) 001 C rin2 010 C df2se out 011 C adc input (after mic amplifier) others C reserved
everest semiconductor confidential ES8388S revision 8 .0 26 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 39 C dac control 17 , default 0011 1000 bit name bit description ld2lo 7 0 C left dac to left mixer disable (default) 1 C left dac to left mixer enable li2lo 6 0 C lin signal to left mixer disable (default) 1 C lin signal to left mixer enable li2lovol 5:3 lin signal to left mixer gain 000 C 6 db 001 C 3 db 010 C 0 db 011 C - 3 db 100 C - 6 db 101 C - 9 db 110 C - 12 db 111 C - 15 db (default) mixboth 2 0 C normal (default) 1 C ri2rovol use li2lovol register 42 C dac control 20 , default 0011 1000 bit name bit description rd2ro 7 0 C right dac to right mixer disable (default) 1 C right dac to right mixer enable ri2ro 6 0 C rin signal to right mixer disable (default) 1 C rin signal to right mixer enable ri2rovol 5:3 rin signal to right mixer gain 000 C 6 db 001 C 3 db 010 C 0 db 011 C - 3 db 100 C - 6 db 101 C - 9 db 110 C - 12 db 111 C - 15 db (default) register 43 C dac control 21 , default 00 0 1 0 000 bit name bit description slrck 7 0 C daclrc and adclrc separate (default) 1 C daclrc and adclrc same lrck_sel 6 master mode, if slrck = 1 then 0 C use dac lrck (default) 1 C use adc lrck offset_dis 5 0 C disable offset (default) 1 C enable offset mclk_dis 4 0 C normal 1 C disable mclk input from pad (default) pdn_adc_anaclk 3 0 C normal (default) 1 C power down adc anaclk pdn_dac_anaclk 2 0 C normal (default) 1 C power down dac anaclk
everest semiconductor confidential ES8388S revision 8 .0 27 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com register 44 C dac control 22 , default 00 00 0 000 bit name bit description offset 7:0 dc offset register 45 C dac control 23 , default 0000 0000 bit name bit description vroi 4 0 C 1.5k vref to analog output resistance (default) 1 C 40k vref to analog output resistance register 48 C dac control 26 , default 0000 0000 bit name bit description lrboth 6 0 C normal (default) 1 C routvol use loutvol loutvol 5:0 lout volume 000000 C - 45db (default) 000001 C - 43.5db 000010 C - 42db 011110 C 0 db 011111 C 1 .5db 10000 1 C 4.5db register 49 C dac control 27 , default 0000 0000 bit name bit description routvol 5:0 rout volume 000000 C - 45db (default) 000001 C - 43.5db 000010 C - 42db 011110 C 0 db 011111 C 1 .5db 10000 1 C 4.5db register 5 3 C test mode , default 0000 0000 bit name bit description testmodeenable 7 writing a0 to this register enables the test mode register 5 6 C adc test control 2 , default 0000 0000 bit name bit description df2se_10db 1 df2se 10 db enable 0 C disable (default) 1 C enable
everest semiconductor confidential ES8388S revision 8 .0 28 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 10. package
everest semiconductor confidential ES8388S revision 8 .0 2 9 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 11. corporate informatio n everest semiconductor co., ltd. no. 1355 jinjihu drive, suzhou industrial park, jiangsu, p.r. china, zip code 215021 ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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